The semiconductor integrated circuit (IC) industry has experienced rapid growth. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC manufacturing are needed.
For example, as the scaling down continues, conventional 6 T (6-transistor) static random access memory (SRAM) cell suffers from stability problems during read and write operations, where the cell is vulnerable towards noise. To overcome such issue, 8 T (8-transistor) SRAM cell designs have been proposed, where write port (write word/bit lines with 6 transistors) are separate from read port (read word/bit lines with 2 transistors). However, existing 8 T SRAM cell is not completely satisfactory. For example, the 6 transistors in the write port in conventional 8 T SRAM cells are often unbalanced or asymmetrical, which often leads to increased Vccmin (minimum operation voltage). Increased Vccmin leads to increased power consumption and hence is not desirable.